verilog how to create linear feedback shift register

The Last (tap) feedback point defines the effective length of the LFSR, after that it would just be a shift register and have no bearing on the feedback sequence.

If you are unsure of the order of the taps, remember that the MSB will always be a feedback point. The first would have a feedback term of: feedback = data ^ data ^ data ^ data With N bits a Maximal LFSR will have (2**N) - 1 states. When considering the implementation of the LFSR, the bit width of the random number and the repeatability of the number need to be considered. Implementation is relatively simple, a shift register with a number of terms XORd together to create the feedback term. Just put it in a loop and let the synthesis tool figure out the logic: module fibonacci_lfsr_nbitĭata_next = Īssign stage = !stage ^ stage Īn LFSR is often the first port of call. Repeating Morgan's example below, but to get a 5 bit number each cycle: module fibonacci_lfsr_5bit(Įdit: Added a new version below which doesn't require you to do the math. However, if you want a new number every clock cycle the other option is to unroll the loop and predict what the number will be in N cycles. If you want an N bit random number you have to run the LFSR for N cycles. The number of bits in the LFSR only set how many values you get before the sequence repeats. More importantly, if you want to make the module support generic bit-widths of the inputs and outputs, you can do so using a parameter on the module and a similar loop for the assignments.As noted in Morgan's answer this will only produce a single random bit. One advantage of coding it using a loop is it is less prone to cut-n-paste typos. I'm not an expert on how the synthesis tools handle this but this (or something similar) should synthesize okay. If you don't want to write out all the values you can use a for loop. This could also be coded using a case statement inside an always block, like this: reg out_reg If the sizes of in and out are really fixed at 8 bits, here is one simple way to do it: module sr(N, in, out) Īssign out = (N = 7) ? :

Verilog how to create linear feedback shift register